In the previous post I posed the question as to what the voltage level would be at ‘d’ node in both of the following cases.

Let’s look at the nmos transistor on the left side. Top end(source or drain ?) is at VDD and gate of this device is at VDD. It is obvious that gate to top-end voltage difference for the nmos transistor on the left end side is zero, which is less than the Vth as Vth is typically few hundreds of mili-volts. Based on our understanding of CMOS theory, top-end junction is in cut-off region with no inversion channel formed.

What about the other junction? That is the gate to lower-end junction. We don’t know initial voltage at ‘d’ node, it is unknown to us and it could be anything. Because of that the gate to low-end junction could have fully formed channel if the gate to low-end difference is more than Vth or it could be cut-off if difference is less than Vth.

Now lets take the case where initial voltage at node ‘d’ is VDD, in which case, gate to this bottom-end voltage difference is zero and this junction is cut-off as well. With both junctions at cut-off, transistor is off and no current flows through transistor. Which means top-end voltage remains at VDD and bottom end voltage remains at it’s initial voltage which is VDD as well.

Now what if node ‘d’ is initially at (VDD-Vth) or lower voltage ? In that case gate to bottom-end junction voltage difference is more than Vth and this junction has inversion channel fully developed. Now we know that when at least one junction is on, the current flows through the transistor. In this case gate to top-end junction is off and gate to bottom-end junction is on, which means transistor is in saturation region and current flows from top-end to bottom-end. What would happen is that, if initial voltage at ‘d’ was less than (VDD-Vth), because of the on transistor, the node ‘d’ will keep charging until it reaches at (VDD-Vth), but right when node ‘d’ reaches (VDD-Vth) the bottom junction will be cut-off as at that point the gate to bottom-end voltage difference will become less than Vth

So you can see that for nmos, when one of the end is at VDD, voltage we can never pass more than (VDD-Vth) voltage to the other end. Which we refer to as weak ‘1’ as it doesn’t fully reach VDD. On the other end of one end of nmos is at VSS, we can fully pass this VSS to the other end as we saw in the case of the nmos on the left side.

I’ll ask you same question which asked for pmos example. What would change if nmos input was VSS.

-SR

In last post the question was posed, what would happen if pmos input were to be VDD. Let’s examine that.

For the pmos on left, the gate and top-end potentials(voltages) are same, both VDD, which means that junction is definitely cut-off. Now what about initial potential for node ‘d’ ? If we were to assume that our initial voltage could only be within the range of VSS to VDD.

Given this assumption, highest voltage bottom-end node ‘d’ could be at is VDD and even then the bottom-end junction will be cutoff as gate and the node ‘d’ would both be at same voltage VDD. If node ‘d’ is at lower voltage than VDD, the junction is still going to be cutoff as in either case gate voltage is going to be higher than the bottom-end voltage and for pmos inversion channel to be formed, the gate voltage has to be lower than the junction voltage by Vth.

So pmos on the left side will always be off, there will be no current passing through this pmos and it will not contribute to any change in initial voltage at node ‘d’.

Reader should be able to extrapolate what would happen to the pmos on the right. Is it going to be same as pmos on left or any different ?

As always, your questions and comments are welcome.

-SR

In the previous post I posed the question as to what the voltage level would be at ‘d’ node in both of the following cases.

Let’s look at the pmos transistor on the left side. Top end(source or drain ?) is at VDD and gate of this device is at VSS. It is obvious that gate to top-end voltage difference for the pmos transistor on the left end side is(VSS) less than the (VDD-Vth) as Vth is typically few hundreds of mili-volts at the most. Based on our understanding of CMOS theory, inversion channel has fully formed at the gate to top-end junction. Now pay attention closely, you will not get this information at anywhere else if you’re just beginning to learn CMOS transistors.

At this stage you might wonder, what about the other junction. That is the gate to lower-end junction. We don’t know initial voltage at ‘d’ node, it is unknown to us and it could be anything. Because of that the gate to low-end junction could have fully formed channel if the gate to low-end difference is less than (VDD-Vth) or it could be cut-off if difference is more than (VDD-Vth).

In either case there is a low-resistance conduction path formed from top-end of this transistor to bottom-end. Why ? Because if both junctions have fully formed channel, it’s obvious there is a path, but even when bottom-end channel is cut-off( also called pinched-off) the carriers still drift through this pinched-off junction under the effect of the electrical field and node ‘d’ keeps getting charged and it’ll get fully charged upto VDD without any problems. It can not go above VDD as that’s when it reaches same potential as the top-end node.

So eventually node ‘d’ for the pmos transistor on left will settle at VDD.

I intentionally refereed to nodes as ‘top-end’ and ‘bottom-end’ as in reality source and drain are reversible for a transistor, but by convention the source is the source of the current carries(electrons) and drain is the node that receives electron. In our case the current follows from top to bottom, which means electrons travel from bottom to top and hence bottom-end is source and top-end is drain.

Now what about pmos transistor on the right side. As you can imagine, the gate to top-end voltage difference is zero ( both at VSS), which means this junction is cut-off. Gate of the pmos transistor needs to be less than one of the ends by Vth amount in order for the channel to form at that junction.

How about initial voltage at node ‘d’. Again, we don’t know what it could be. But what we know is that as long as it’s more than Vth, the gate to bottom-end junction channel will form and as long as one junction channel forms, the current will flow. The key is node ‘d’ can never fall below Vth, because right when it reaches a fraction below Vth, that junction channel will be cut-off and we know that gate to top-end junction channel is already cut-off, and with both junctions cut-off, transistor turns off and no more current can flow through it and no more voltage difference takes place.

So bottom-end in right side transistor can never fall below Vth.

We learn two important lessons about pmos characteristics. If one of the end of pmos is at VDD, we can fully pass VDD level to other end of pmos by biasing gate voltage to be VSS. But if one of the end of pmos transistor is at VSS, no matter what you do you can not bias other end to VSS, other end can not fall below Vth.

We say that pmos passes strong ‘1’ (VDD) but it can only pass weak ‘0’ (VSS).

What would happen if the gate is at VDD in both cases ?

-SR

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Lets go back to CMOS basics. What would be the voltage at node ‘d’ in both cases below ? Why ?

-SR

 

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CMOS transistor has three operating regions. Following are the most commonly quoted equations characterizing these regions.
1) Cutoff, Vgs < Vth 2) Linear, Vgs > Vth & 0 < Vds < Vgs -Vth 3) Saturation, Vds > Vgs – Vth

It could be difficult to grasp these equations unless you really understand what’s going on these three different regions. An alternate way to think of CMOS transistor operating regions is following.

CMOS transistor channel has two ends. Source end and Drain end. Channel is fully formed only if both ends are open, or in other words channel is fully open if it has fully formed at both ends. One can imagine it as a conduit where flow can happen only if conduit’s both ends are open.

When both ends of channel are closed, which is the case when Vgs < Vth and Vgd < Vth, transistor is non-conducting and is said to be in cut-off. When channel is formed at both ends it's in linear region and it acts as normal conductor where Voltage difference between two ends modulate the current flow. Channel depth (controlled by the amount of voltage difference above Vth) could be different at both ends but the point is channel is formed at both ends in linear region. Now when channel is shut-off at drain end, which is popularly called 'pinched-off' channel, the behavior of current flow changes. One would imagine that shut-off channel at one end means no through current, but that's not the case, even with pinched off channel there is drift current flowing because of the strong filed at drain, which keeps current conduction on. It's just that current conduction in saturation region is independent of the voltage difference between drain and source as channel is no more behaving like a resistor between drain and source any more(pinched-off conduit). Coming back to the point, it is simpler to view channel in terms of two ends. Source end and Drain end. Channel is open at either of the end of the voltage difference at that end is greater than threshold voltage. 1) Cutoff, both ends of channel off... Vgs < Vth & Vgd < Vth 2) Linear, both ends of channel on, Vgs > Vth & Vgd > Vth, Vgs could be same as Vgd or they could differ
3) Saturation, drain end channel off, Vgs > Vth but Vgd < Vth Just think in terms of Vgs & Vgs, don't stress Vds at least to understand the transistor operating regions. You can refer to the visual representation here : Wikipedia.

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