# XOR gate using 2:1 MUX

XOR gate is kind of a special gate. We are familiar with the truth table of the XOR gate. Figure1. XOR gate

We often use symbol OR symbol ‘+’ with circle around it to represent the XOR operation. There is an alternate way to describe XOR operation, which one can observe based on the truth table. One of the best way to find out a equation representation of any table is to use K-maps. Figure 2. XOR K-map.

Out = A * (B)bar + (A)bar * B

Now having this equation at our hand it is easier to start with 2:1 MUX equation and convert it to XOR equation that we want.

2:1 MUX equation is :

Out = S * A + (S)bar * B

We can see that if we replace A with (B)bar, we get what we want.

Out = S * (B)bar + (S)bar * B

This is the XOR between S and B.

Following is the figure for the same. Figure 3. XOR using 2:1 MUX

Next time we will work on XNOR gate.

-SS

# A NOR gate using a 2:1 MUX

As previously discussed we start with the equation for 2:1 MUX like following. MUX has two inputs A and B and select pin is S and output pin Out

Out = S * A + (S)bar * B

As we want to make a NOR gate we are looking for equation of the form

Out = (A + B)bar

Just keep in mind taht we don’t have to get exact same equation with same pins, we could use any of teh three input pins A, B and S.

Where do we start ? This is something I did not mentioned while forming a NAND gate, but this applies to both NAND and NOR gate. We have already made AND gate, OR gate and inverter using 2:1 MUX. You can use AND gate and inverter and combine them to make NAND. Similarly you can use OR gate and inverter and combine them to make NOR gate. That would be one option to come up with NOR gate using 2:1 MUX.

Here we will try to come up with NOR gate using alternative way.

Going back we have

Out = S * A + (S)bar * B and we want to convert this to a NOR equation.

We want form

Out = (A + B)bar which is same as

Out = (A)bar * (B)bar

In our 2:1 MUX equation, you can easily see that we need to have (B)bar in place of B and we need to zero out the ‘S * A’ term.

We can achieve both by tying (B)bar in place of B and tying 0 to input A.

Out = S * 0 + (S)bar * (B)bar

Out = (S)bar + (B)bar

Out = (S + B)bar [ DeMorgan’s rule]

That is our NOR gate. Figure NOR using 2:1 MUX

By now you should have become expert at this process. We will look at XOR gate in next  example. Please provide your feedback, ideas and critique, through various communications channels, like comments, contact form etc. I look forward to hearing from you.

-SS

# Make a NAND gate using a MUX

Lets start with the equation of a 2:1 MUX, with input pins A and B, select pin S and output pin Out.

Out = S * A + (S)bar * B

We need to come up with a NAND gate and equation of a NAND gate is of the form :

Out = (A * B)bar or  Our = (A)bar + (B)bar [ using De Morgan’s rule]

Given the form of equations that we have to begin with it looks like we might have a better shot of converting. This is purely a guess.

Out = S * A + (S)bar * B  to the latter form of NAND equation [ Out = (A)bar + (B)bar]

If we actually tie (A)bar instead of A pin to the MUX and if we tie 1 to the B input

Out = S * (A)bar + (S)bar * 1

Out = S * (A)bar + (S)bar

Now lets prove that this is same as Out = (A)bar + (S)bar

Out = S * (A)bar + (S)bar

(Out)bar = (S * (A)bar + (S)bar) bar

(Out)bar = (S * (A)bar)bar * ((S)bar)bar

(Out)bar = (S * (A)bar)bar * S

(Out)bar = ((S)bar + ((A)bar)bar) * S

(Out)bar = ((S)bar + A) * S

(Out)bar = (S)bar * S + A * S

(Out)bar = 0 + A * S

(Out)bar = A * S

Out = (A * S)bar

Our guess worked and we have a  NAND gate by tying (A)bar instead of A and tying B to 1. Figure NAND using 2:1 MUX

We will look at NOR gate in next post.

-SS

# Make an OR gate using a MUX

We start with the equation of 2:1 MUX, where inputs to the mux are ‘A’ and ‘B’. Select is ‘S’ and output pin is ‘Out’.

Out = S * A + (S)bar * B

We need to come with an OR gate, hence we need to keep the ORing term ‘+’ in the equation, this means that we can not tie ‘S’ to 1 or 0. Because of tie ‘S’ to 1 or 0, one of the terms in the equation of MUX will have a product of 0 and that term will disappear.

What I mean is :

If we tie ‘S’ to 0.  Out = 0 * A + (0)bar * B = 0 + B = B

If we tie ‘S’ to 1.  Out = 1 * A + (1)bar * B = A + 0 * B = A

In both cases we look the ORing term ‘+’.

Same way, we can not tie either ‘A’ or ‘B’ to zero to maintain the ‘+’ term.

Out = S * 1 + (S)bar * B

Out = S + (S)bar * B

This is what we end up with. We really want : Out = S + B.

If you are a master at boolean algebra or digital logic, you can look at equation

Out = S + (S)bar * B

and tell that it’s equivalent to

Out = S + B

But do not worry. We’ll prove that to be the case.

Out = S + (S)bar * B

(Out)bar = (S + (S)bar * B)bar    [ taking bar of both sides ]

(Out)bar = (S)bar * ((S)bar * B)bar  [ Applying De-morgan’s rule on right hand side ]

(Out)bar = (S)bar * (S + (B)bar)   [Applying De-morgan’s rule on right most term]

(Out)bar = (S)bar * S + (S)bar * (B)bar   [Expanding right hand side]

(Out)bar = 0 + (S)bar * (B)bar   [Simplifying first term on right hand side]

(Out)bar = (S)bar * (B)bar

(Out)bar = (S + B)bar          [Applying De-morgan’s rule on right hand side]

Out = S + B     [Taking bar of both sides]

Hence we prove that if we tie input ‘A’ to 1, for a 2:1 MUX, we get an OR gate. Figure 1. OR gate using 2:1 MUX.

Next we will look at the NAND gate using 2:1 MUX.

-SS

# Make an AND gate using MUX

As we discussed in previous post, we can start with the equation of the MUX and reduce it down to equation of an AND gate like following.

For a 2:1 MUX with input A and B and select S and output Out, following is the equation.

Out = S * A + (S)bar * B

We can see that first product term in the sum of products on right hand side is actually an AND operation. All we need to do is zero out the second product term. We can achieve this by making B as ‘0’. We can tie B input of MUX to zero.

Out = S * A + (S)bar * 0

Out = S * A + 0

Out = S * A

Thus we can get an AND gate by tying B input of MUX to zero, resulting circuit is AND gate which ANDs input A and mux select S.

Following figure shows this arrangement. Figure 1. AND gate using 2:1 MUX

How about an OR gate using 2:1 MUX ?

-SS

# Make an inverter using mux

One of the very popular digital design interview questions is how to make a gate using a 2:1 multiplexer, or a mux as we usually refer to. This tests your knowledge of the basic boolean logic or boolean algebra.

Key is to know basic manipulation rules of boolean algebra. There are several ways to deal with this question. The way I would start is from the equation of mux. Reduce it to the equation of a gate that you want.

Equation of a mux with inputs A & B, select S and output Out is following.

Out = S * A + (S)bar * B

We know that equation of inverter is :

Out = (In)bar

We can see that equation of mux has one ‘bar’ term, which is ‘(S)bar’. We just need to keep this bar term and we need to zero out the other terms ‘S * A’. We can achieve that by tying A to ‘0’. We can keep ‘(S)bar’ term by tying B to ‘1’.

Out = S * A + (S)bar * B

Tie A to ‘0’ and B to ‘1’.

Out = S * 0 + (S)bar * 1

Out = 0 + (S)bar

Out = (S)bar

Out inverts S.

Here is the figure for such a circuit. Figure 1. Inv using 2:1 MUX

How can we make an AND gate now ?

-SS.

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# Transistor modes during inverter operation. High input.

Last stage to consider in this series of posts is when inverter input is high. Following figure shows this condition. Figure 1. Inverter with input at VDD.

You can easily tell that pmos gate to source voltage difference is zero. Both are at VDD, hence pmos can not be active, it can only be in saturation or cut-off depending upon the node ‘out’ voltage.

Nmos gate is at VDD and gate to source is forward biased and channel is formed. If node ‘out’ was at VDD to begin with, nmos would start out in saturation as gate to drain would have been cut-off and as node ‘out’ continues to discharge, the nmos would enter linear region and would remain there for rest of discharge. On the other hand pmos would start out in cut-off region with both junction cut-off and would remain so for rest of the time.

Will discuss few popular questions with answer in next series of posts.

-SS

# Transistor modes during inverter operation. Rising input.

Previously we looked at the transistor modes during inverter operation, when input is at VSS. Now lets look at the transistor modes when input is rising and is in the range Vth to VDD – Vth. Figure 1. Transistor modes in inverters.

We can see that for nmos gate voltage is higher than Vth and source being at VSS, the Vgs for nmos is greater than Vth and inversion channel is formed at gate to source junction. How about gate to drain junction. Again it will depend on what the initial voltage is at node ‘out’. If node ‘out’ voltage is such that Vgd is higher than Vth, the inversion channel extends to gate to drain junction for nmos and nmos is in linear region. But if node at ‘out’ is equal or greater than input/gate voltage for nmos the Vgd is going to be less than Vth or in other words Vds is going to be greater than Vgs – Vth and the gate to drain junction is going to be in cut-off, with pinched off channel and hence nmos in saturation.

When input is rising for an inverter, most likely the node ‘out’ is going to close to VDD to begin with and node ‘out’ will be discharged through nmos, hence to begin with the nmos is going to be in saturation and then it’ll flip to linear region as discharge of ‘out’ continues.

Lets look at the pmos now. Given that Vin is less than VDD – Vth, pmos gate to source junction has inversion channel formed. Again gate to drain for pmos will depend and if node ‘out’ is close to VDD, the gate to drain junction will also have inversion channel formed, which means pmos is going to start out in active region (assuming ‘out’ to be at VDD to begin with) and very soon ‘out’ will match with Vin and fall below Vin, which means gate to drain junction will be cut-off and pmos will flip to saturation.

Keep in mind well that nmos being in active or saturation all along is the reason, current will continue to fall through the nmos and node ‘out’ will discharge. But we also noticed that pmos is also conducting all along, which mean there could be current contention at node ‘out’ and depending upon which one is the stronger source and sink of current, will decide how fast node ‘out’ discharges.

Another thing to notice is that for this range of input voltage Vin, both transistors are on. When pmos or nmos is on, it provides very low resistive path. We have a very low resistive path from VDD to VSS !! What does it mean ? It means a large current would from from VDD to VSS, which is also called crowbar current or rush-through current. Such current could be very damaging to circuit and causes excessive power dissipation.

This is the reason, we want inverter to be in this range for least amount of time possible.  Given the finite rise time of input signals it is inevitable to avoid this region, but one should take care to minimize this region. What can you do to minimize the time inverter stays in the region where input voltage of inverter is within the range Vth to VDD – Vth ??

-SR

# Transistor modes during inverter operation. Low input.

In previous post I posed a question as what modes pmos and nmos transistors are during normal inverter operation. Lets answer this question.

For the inverter input we can consider three different possibilities. Lets call input Vin.

case 1) VSS <= Vin < Vth

case 2) Vth < Vin < (VDD – Vth)

case 3) (VDD – Vth) < Vin <= VDD Figure 1. Inverter charging output node high

It will become apparent later on as to why we choose these ranges. Lets think of first case where input is between the range VSS and Vth. For nmos device, source is tied to ground and if gate voltage is less than Vth we know gate to source junction is cut-off. What about gate to drain junction of nmos ? We don’t know initial voltage at node ‘out’. It could be anywhere between VSS and VDD, but it doesn’t matter, no matter what voltage node ‘out’ is, nmos gate to drain junction is also cut-off as gate voltage is less than Vth. In other words, no matter what voltage node ‘out’ (drain of nmos) is, Vds will always be greater than or equal to (Vgs – Vth) [ Because in this case Vgs is at most Vth, hence (Vgs – Vth) can at most be zero and Vds can not be less than zero ].

Given that both nmos junction are cut-off, there is no channel formed in nmos and nmos is in cut-off for sure.

What about pmos ? Pmos source is tied to VDD and pmos gate is at VSS, hence pmos Vgs is < (VDD – Vth) and channel is formed at pmos gate to source junction. At least one end channel formed, so pmos is definitely not in cut-off. As mentioned earlier node ‘out’ could be at any unknown voltage at initial stage between VSS and VDD. Essentially pmos could be either in active region or saturation and it will start conducting current and start charging the load capacitance it sees at node ‘out’.

If node ‘out’ initial voltage is VSS, the gate to drain voltage difference is zero for pmos and no channel is formed at gate to drain junction for pmos and hence pmos will be in saturation. Remember key to a transistor being in saturation is having a pinched off channel, the channel that is formed only at one of the junctions.

As soon as node ‘out’ reaches Vth or above, or to be more precise the voltage difference the gate to drain voltage difference will reach Vth, the channel will extend at this junction as well. In other words as soon as (Vgs + Vth) < Vds, the pmos will have inversion channels at both junctions and pmos will be in active or ohmic region now. Now onwards drain voltage( node ‘out’ voltage) is only increasing as pmos continues to charge the output load, hence pmos will remain in active region for rest of the time. It will only go back to saturation only if Vgd for pmos increases to more than -Vth.

We conclude that for the case where input voltage of inverter Vin is between VSS and Vth, the nmos is in cutoff and pmos could be either in saturation or active region, but in normal scenario it will be transitioning from saturation to active region.

We’ll consider case 2 & 3 in next post. Please watch for the next post. Your feedback and comments are always appreciated and are most welcome.

-SR