In previous post I posed a question as what modes pmos and nmos transistors are during normal inverter operation. Lets answer this question.
For the inverter input we can consider three different possibilities. Lets call input Vin.
case 1) VSS <= Vin < Vth
case 2) Vth < Vin < (VDD – Vth)
case 3) (VDD – Vth) < Vin <= VDD
Figure 1. Inverter charging output node high
It will become apparent later on as to why we choose these ranges. Lets think of first case where input is between the range VSS and Vth. For nmos device, source is tied to ground and if gate voltage is less than Vth we know gate to source junction is cut-off. What about gate to drain junction of nmos ? We don’t know initial voltage at node ‘out’. It could be anywhere between VSS and VDD, but it doesn’t matter, no matter what voltage node ‘out’ is, nmos gate to drain junction is also cut-off as gate voltage is less than Vth. In other words, no matter what voltage node ‘out’ (drain of nmos) is, Vds will always be greater than or equal to (Vgs – Vth) [ Because in this case Vgs is at most Vth, hence (Vgs – Vth) can at most be zero and Vds can not be less than zero ].
Given that both nmos junction are cut-off, there is no channel formed in nmos and nmos is in cut-off for sure.
What about pmos ? Pmos source is tied to VDD and pmos gate is at VSS, hence pmos Vgs is < (VDD – Vth) and channel is formed at pmos gate to source junction. At least one end channel formed, so pmos is definitely not in cut-off. As mentioned earlier node ‘out’ could be at any unknown voltage at initial stage between VSS and VDD. Essentially pmos could be either in active region or saturation and it will start conducting current and start charging the load capacitance it sees at node ‘out’.
If node ‘out’ initial voltage is VSS, the gate to drain voltage difference is zero for pmos and no channel is formed at gate to drain junction for pmos and hence pmos will be in saturation. Remember key to a transistor being in saturation is having a pinched off channel, the channel that is formed only at one of the junctions.
As soon as node ‘out’ reaches Vth or above, or to be more precise the voltage difference the gate to drain voltage difference will reach Vth, the channel will extend at this junction as well. In other words as soon as (Vgs + Vth) < Vds, the pmos will have inversion channels at both junctions and pmos will be in active or ohmic region now. Now onwards drain voltage( node ‘out’ voltage) is only increasing as pmos continues to charge the output load, hence pmos will remain in active region for rest of the time. It will only go back to saturation only if Vgd for pmos increases to more than -Vth.
We conclude that for the case where input voltage of inverter Vin is between VSS and Vth, the nmos is in cutoff and pmos could be either in saturation or active region, but in normal scenario it will be transitioning from saturation to active region.
We’ll consider case 2 & 3 in next post. Please watch for the next post. Your feedback and comments are always appreciated and are most welcome.