Transistor modes during normal inverter operation.

When you think of operation of an inverter, we usually think of input and output binary states. Meaning, we know that if input is low, output is going to be high and vice versa. It might be worthwhile to think, what modes transistors are in during the steady state of inverter and during transition from low to high and vice versa. Transistor modes being, cutoff, linear and saturation. This is a different perspective of looking at the MOS transistor operations in logic gates, which is helpful in getting better overall understanding of MOS circuits.

Lets start with a case where input is low for an inverter as shown in figure below. If input is low (VSS) we know that NMOS Vgs is zero. Because both gate and source are at VSS, which means Vgs < Vth and NMOS is in cutoff. What about PMOS ?

Figure 1. Inverter with input at VSS

We shall discuss the answer in next post. Feel free to comment about your ideas.


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