Following is the case with gate tied to VSS for the nmos. Let’s look at the first transistor on the left side.
For this transistor top end is at VDD and gate is at VSS, which means top end junction is cut-off, remember for nmos junction to be not cut-off the gate to terminal voltage difference has to be > vth. In our case voltage difference between gate to the top end terminal is negative. As usual for bottom end terminal we can assume it to be either VSS or VDD. In either case gate to bottom end voltage difference is going to be less than Vth. Hence both top end and bottom end junctions are going to be cut off and transistor is going to be turned off. One can argue what if node ‘d’ initial value is intermediate between VSS and VDD, even in that case the gate to bottom end voltage difference is going to be less than Vth and still transistor is going to be off.
Let’s consider transistor on the right side. You can see that top end is going to be cut-off as gate to top end voltage difference is zero which is less than Vth. Bottom end situation is going to be same as first transistor. This transistor is going to be off, no current will flow through either of transistors and node ‘d’ will maintain it’s initial state.
Any comments ? Questions ?