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In previous post we saw how we use a look-up table based simple modelling of devices for getting timing-arcs or delay-arcs through the devices. These arcs are nothing but input-output pin pair delay values. Now we can look at how wire delays are modeled in STA.

In spice modelling, again wires are represented through a complex mathematical function based models are used ( Think matrices, nodal analysis ), which accurately models wires behavior and you can see waveform propagation happening through wires based on the characteristics of the wires and one can measure delays through probing the waveforms in question during the dynamic timing analysis.

Similar to devices, idea is to come up with a simplistic modelling of wires which can give us reasonably accurate delay values through the wires, for static timing analysis. There are several models available for wires, but one such model ‘Elmore delay’ has been widely used in industry because of its simplicity and relative accuracy. We’ll talk more about this Elmore delay model here.

If you want to find out wire delay from point ‘a’ to point ‘c’, we can get it using following formula.
RC(ac)= R1C1 + (R1+R2)C2.
If there are N stages, general formula is like following.
RC(an)= R1C1 + (R1+R2)C2 + (R1+R2+R3)C3 + … + (R1+R2+R3+….+RN)CN.

Hope you get the idea.

In practice any segment of wire is broken into small pieces, like the R1, R2.. RN in the picture and Elmore delay formula is used to come up with the real wire delay numbers. Here I’ve explained very simplified concept of the wiredelay. Later on we’ll discuss more about various complexities that we’ve to deal with when we want to accurately come up with wire delays.

-SR

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In timing analysis we are interested in mainly delay through standard gates and slopes or transition values of signals at various nodes in circuit. These delays and slopes dictate what speed your circuit will run without any functional issues.STA stands for Static Timing Analysis. Static as opposed to dynamic timing analysis. One can choose to do either static or dynamic timing analysis. So what is the difference ?

Main difference between two methods lies in the way circuit components are modeled. Dynamic timing analysis is done through dynamic simulation of the circuits. Spice simulation that you might be familiar with. While static timing analysis is done through a look-up table method, no dynamic simulation is performed.

For standard cells(logic gates), delay through the cell primarily depends on three factors: Strength of the cell, input signal slope and output pin load.

For dynamic analysis spice simulation of the whole circuit in question is carried out. In spice simulation circuit devices are modeled through mathematical functions. Think of matrices and nodal analysis. To state in simple terms, spice model has mathematical functions of various parameters of the device.

A standard cell is modeled through math functions where by delay through the cell is represented as a function of the input signal slope, output pin load and the strength of the cell in question.

If you look at the following simple figure of a buffer, it’ll be provided input wave from with certain slope and on output a waveform with certain slope will be observed. The delay of the cells is measured through these wave forms at 50% rise/fall time as shown in the picture.

While in static timing analysis, we don’t simulate, but the device behavior is represented as a table and based on the actual input parameter values we just look up the table to find delay through the cell.
Lets say the size of buffer in above figure is B and for this B size we’ve following extensively simplified version of the table.

Input Slope	Output Load	Delay
0.05ns	0.2pf	0.05ns
0.1ns	0.2pf	0.075ns

As it was mentioned previously the delay through the cell depends on the input waveform slope and output pin load. When the timing analysis is done, based on the current values of input slope and output load we simply pick the correct entry from the table there we’ve delay number through the cell. That simple !

Of course this is simplistic analysis to give you a very high level idea of the difference between static v/s dynamic timing analysis.

So what about wires in the circuit ? That we’ll cover in next post.

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Let’s look at the hold failure or the min delay constraint in depth here. Like setup, there is a ‘Hold’ requirement for each sequential element (flop or a latch). That requirement dictates that after the assertion of the active/capturing edge of the sequential element input data needs to be stable for a certain time/window.

If input data changes within this hold requirement time/window, output of the sequential element could go meta-stable or output could capture unintentional input data. Therefor it is very crucial that input data be held till hold requirement time is met for the sequential in question.

In our figure below, data at input pin ‘In’ of the first flop is meeting setup and is correctly captured by first flop. Output of first flop ‘FF1_out’ happens to be inverted version of input ‘In’.

As you can see once the active edge of the clock for the first flop happens, which is rising edge here, after a certain clock to out delay output FF1_out falls. Now for sake of our understanding assume that combinational delay from FF1_out to FF2_in is very very small and signal goes blazing fast from FF1_out to FF2_in as shown in the figure below.

In real life this could happen because of several reasons, it could happen by design (imagine no device between first and second flop and just small wire, even better think of both flops abutting each-other ), it could be because of device variation and you could end up with very very fast device/devices along the signal path, there could be capacitance coupling happening with adjacent wires, favoring the transitions along the FF1_out to FF2_in, node adjacent to FF2_in might be transitioning high to low( fall ) with a sharp slew rate or slope which couples favorably with FF2_in going down and speeds up FF2_in fall delay.

In short in reality there are several reasons for device delay to speed up along the signal propagation path. Now what ends up happening because of fast data is that FF2_in transitions within the hold time requirement window of flop clocked by clk2 and essentially violates the hold requirement for clk2 flop.

This causes the the falling transition of FF2_in to be captured in first clk2 cycle where as design intention was to capture falling transition of FF2_in in second cycle of clk2. It looks as if FF2_in falling transition races through the first clk2 cycle, whereas intention was for FF2_in fall to be captured during the next clock cycle of clk2. This is the reason, hold or min failures are often referred to as races, as data is essentially racing through.

As you can see in the waveform, the ‘Out’ node actually captures the low value of FF2_in, although the intention was to capture the high value. What is not shown in the figure is that, when hold time is violated, the ‘Out’ node is most likely to go meta-stable( you can refer to previous post about setup failure) and get into an pseudo stable state where it’s swinging between and high and low rails for a while before settling to binary high or low value. It could take a really long time( more than a cycle !) for the flop output node to settle. Consequences are similar in the sense that down stream logic could sample false data and one would have functional corruption.

In a normal synchronous design where you have series of flip-flops clocked by a grid clock(clock shown in figure below) intention is that in first clock cycle for clk1 & clk2, FF1_out transitions and there would be enough delay from FF1_out to FF2_in such that one would ideally have met hold requirement for the first clock cycle of clk2 at second flop and FF2_in would meet setup before the second clock cycle of clk2 and when second clock cycle starts, at the active edge of clk2 original transition of FF1_out is propagated to Out.

Now if you notice there is skew between clk1 and clk2, the skew is making clk2 edge come later than the clk1 edge ( ideally we expect clk1 & clk2 to be aligned perfectly, that’s ideally !! ).

In our example this is exacerbating the hold issue, if both clocks were perfectly aligned, FF2_in fall could have happened later and would have met hold requirement for the clk2 flop and we wouldn’t have captured wrong data !! Your comments and questions are welcome.

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In last post we looked at general signal propagation from one flop to another and we talked at higher level of max delay or setup constraint. Let’s look at max delay constraint in more depth so it is very clear before we move onto min delay or hold constraint.

Following figure describes visually a setup failure. As you can see that first flop releases the data at the active edge of clock, which happens to be the rising edge of the clock. FF1_out falls sometime after the clk1 rises.

The delay from the clock rising to the data changing at output pin is commonly referred to as clock to out delay. There is finite delay from FF1_out to FF2_in through some combinational logic for the signal to travel. After this delay signal arrives at second flop and FF2_in falls. Because of large delay from FF1_out to FF2_in, FF2_in falls after the setup requirement of second flop, indicated by the orange/red vertical dotted line.

This means input signal to second flop FF2_in, is not held stable for setup time requirement of the flop and hence this flop goes meta-stable and takes a long time before settling to the correct value. In theory it could take upto one clock cycle or even more than a clock cycle to resolve the meta-stability, which means flop output could be in the unknown state for one full clock cycle or even more. This means down stream logic( down stream flop or latches) capture wrong data and your state machine is corrupted.

As you can see one would’ve expected ‘Out’ node to go low but it doesn’t because of setup time or max delay failure at the input of the second flop. Setup time requirement dictates that input signal be steady during the setup window ( which is a certain time before the clock capture edge ).

Another possibility is that if input FF2_in, doesn’t fall(change) near the closing edge of the flop, but because of very large delays from FF1_out, it just falls much later than the second rising edge of the clock, in which case, the second flop wouldn’t go meta-stable, but it will just capture ‘1’ to the input, which would be a wrong value to be captured and could cause downstream functional failure.

As mentioned earlier if we reduce frequency, our cycle time increases and eventually FF2_in will be able to make it in time and there will not be a setup failure. Also notice that a clock skew is observed at the second flop.

The clock to second flop clk2 is not aligned with clk1 anymore and it arrives earlier, which exacerbates the setup failure. This is a real world situation where clock to all receivers will not arrival at same time and designer will have to account for the clock skew. We’ll talk separately about clock skew in details in later posts.

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Getting a solid grasp of static timing analysis in digital circuits can be a very big challenge. It usually takes quite a bit of experience. In my view it’s not covered very well in school, and because of that it’s more difficult for new engineers.
I’ll attempt to cover this topic in depth here. We’ll start with most simplest case, which is a basic flip-flop timing path.

In general digital circuits have two types of elements,
1) combinational elements which include logic gates like, NAND gate, NOR gate, COMPLEX gate etc..
2) storage elements or memory elements, which are either flip-flops or latches. Flip-flops, which will be abbreviated as flops, are edge triggered memory elements, while latches are level sensitive memory elements.

Following is a simple structure where output of a flop goes through some stages of combinational logic, represented by pink bubble and is eventually samples by receiving flop. Receiving flop, which samples the FF2_in data, poses timing requirements on the input data signal.

The logic between FF1_out to FF2_in should be such that signal transitions could propagate through this logic fast enough to be captured by the receiving flop. For a flop to correctly capture input data, the input data to flop has to arrive and become stable for some period of time before the capture clock edge at the flop.

This requirement is called the setup time of the flop. Usually you’ll run into setup time issues when there is too much logic in between two flop or the combinational delay is too small. Hence this is sometimes called max delay or slow delay timing issue and the constraints is called max delay constraint.

In figure there is max delay constraint on FF2_in input at receiving flop. Now you can realize that max delay or slow delay constraint is frequency dependent. If you are failing setup to a flop and if you slow down the clock frequency, your clock cycle time increases, hence you’ve larger time for your slow signal transitions to propagate through and you’ll now meet setup requirements.

Typically your digital circuit is run at certain frequency which sets your max delay constraints. Amount of time the signal falls short to meet the setup time is called setup or max, slack or margin. There is flip side to max delay constraint which is min or fast delay constraint.

It more interesting and difficult to understand hence will cover in next post. Following figure shows the data propagation from input to the output of the flop and through combinational delay to the input of next flop.

Be aware that data FF1_out potentially changes( if ‘in’ chnages ) on the active/capture edge of the flop, in following case we’ve assumed flops to be rising edge triggered.

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