Dynamic gates use clock for their normal operation as opposed to the static gates, which don’t use clocks.

Dynamic gates use NMOS or PMOS logic. It doesn’t use CMOS logic like regular static gates. Because it uses either NMOS or PMOS logic and not CMOS logic, it usually has fewer transistors compared to static gates. Although there are extra transistors given that it uses clocks.

Figure : NMOS pull down logic for NOR gate.

The figure shows the pull down NMOS logic for a NOR gate. This pull down structure is used in the dynamic gates.

How dynamic gates work :

In static gates, inputs switch and after a finite input to output delay, output possibly switches to the expected state.

Figure : Dynamic NOR gate.

As you can see in the figure above, dynamic gate is made using NMOS pull down logic along with clock transistors on both pull up and pull  down paths.

We know that clock has two phases, the low phase and the high phase. Dynamic gate has two operating phases based on the clock phases. During the low clock phase, because of the pmos gate on the pull up network, the output of dynamic gate is pre-charged to high phase. This is the pre-charge state of dynamic gate.

When the clock is at high phase, the output of dynamic gate may change based on the inputs, or it may stay pre-charged depending on the input. The phase of the dynamic gates, when the clock is high, is called the evaluate phase. As it is essentially evaluating what the output should be during this phase.

Figure : Dynamic NOR waveforms when input ‘A’ is high.

As seen in the waveforms above, as soon as CLK goes low, it pre-charges output node ‘Out’ high. While in the pre-charge state, NOR input ‘A’ goes high. When CLK goes high, and evaluation phase begins, ‘Out’ is discharged to low as input ‘A’ is high. Input ‘B’ is not shown in the waveform as it is not relevant to this case.

If both inputs ‘A’ and ‘B’ were to remain low, output node would be held high during the pre-charge.

This technique of always priming or pre-charging output to be with, is a way to minimize  switching of the output node, because if with a new set of inputs, output was supposed to be high, it wouldn’t have to switch, as it is already pre-charged. Output  only has to switch in the case where it has to be low.

But obviously such reduction in  output  switching doesn’t come free, as it means introducing the clocks and  the extra pre-charge face, where output is not ready to be sampled.

One of the biggest concerns with dynamic gates, is the crowbar current. It needs to be ensured that the clock input to the pull up and pull down is the same node, because of pull up and pull down clocks are coming from different sources, there is a higher likelihood of both pull up and pull down transistors to be on at the same time and hence the crowbar current.

Dynamic gates burn more power because of the associated clocks. Clock signal switches continuously, hence there is more dynamic power dissipated.

When it comes to doing digital circuit design, one has to know how to size gates. The idea is to pick gate sizes in such a way that it gives the best power v/s performance trade off. We refer to concept of ‘fanout’ when we talk about gate sizes. Fanout for CMOS gates, is the ratio of the load capacitance (the capacitance that it is driving) to the input gate capacitance. As capacitance is proportional to gate size, the fanout turns out to be the ratio of the size of the driven gate to the size of the driver gate.

Fanout of a CMOS gate depends upon the load capacitance and how fast the driving gate can charge and discharge the load capacitance. Digital circuits are mainly about speed and power tradeoff. Simply put, CMOS gate load should be within the range where driving gate can charge or discharge the load within reasonable time with reasonable power dissipation.

Our aim is to find out the nominal fanout value which gives the best speed with least possible power dissipation. To simplify our analysis we can focus on the leakage power, which is proportional to the width or size of the gate. Hence our problem simplifies to, how can we get the smallest delay through gates, while choosing smallest possible gate sizes.

Typical fanout value can be found out using the CMOS gate delay models. Some of the CMOS gate models are very complicated in nature. Luckily there are simplistic delay models, which are fairly accurate. For sake of comprehending this issue, we will go through an overly simplified delay model.

We know that I-V curves of CMOS transistor are not linear and hence, we can’t really assume transistor to be a resistor when transistor is ON, but as mentioned earlier we can assume transistor to be resistor in a simplified model, for our understanding. Following figure shows a NMOS and a PMOS device. Let’s assume that NMOS device is of unit gate width ‘W’ and for such a unit gate width device the resistance is ‘R’. If we were to assume that mobility of electrons is double that of holes, which gives us an approximate P/N ratio of 2/1 to achieve same delay(with very recent process technologies the P/N ratio to get same rise and fall delay is getting close to 1/1). In other words to achieve the same resistance ‘R’ in a PMOS device, we need PMOS device to have double the width compared to NMOS device. That is why to get resistance ‘R’ through PMOS device device it needs to be ‘2W’ wide.

Figure 1. R and C model of CMOS inverter

Our model inverter has NMOS with width ‘W’ and PMOS has width ‘2W’, with equal rise and fall delays. We know that gate capacitance is directly proportional to gate width. Lets also assume that for width ‘W’, the gate capacitance is ‘C’. This means our NMOS gate capacitance is ‘C’ and our PMOS gate capacitance is ‘2C’. Again for sake of simplicity lets assume the diffusion capacitance of transistors to be zero.

Lets assume that an inverter with ‘W’ gate width drives another inverter with gate width that is ‘a’ times the width of the driver transistor. This multiplier ‘a’ is our fanout. For the receiver inverter(load inverter), NMOS gate capacitance would be  a*C as gate capacitance is proportional to the width of the gate.

Figure 2. Unit size inverter driving ‘a’ size inverter

Now let’s represent this back to back inverter in terms of their R and C only models.

Figure 3. Inverter R & C model

For this RC circuit, we can calculate the delay at the driver output node using Elmore delay approximation. If you can recall in Elmore delay model one can find the total delay through multiple nodes in a circuit like this : Start with the first node of interest and keep going downstream along the path where you want to find the delay. Along the path stop at each node and find the total resistance from that node to VDD/VSS and multiply that resistance with total Capacitance on that node. Sum up such R and C product for all nodes.

In our circuit, there is only one node of interest. That is the driver inverter output, or the end of resistance R. In this case total resistance from the node to VDD/VSS is ‘R’ and total capacitance on the node is ‘aC+2aC=3aC’. Hence the delay can be approximated to be ‘R*3aC= 3aRC’

Now to find out the typical value of fanout ‘a’, we can build a circuit with chain of back to back inverters like following circuit.

Figure 4. Chain of inverters.

Objective is to drive load CL with optimum delay through the chain of inverters. Lets assume the input capacitance of first inverter is ‘C’ as shown in figure with unit width. Fanout being ‘a’ next inverter width would ‘a’ and so forth.

The number of inverters along the path can be represented as a function of CL and C like following.

Total number of inverters along chain D = Loga(CL/C) = ln(CL/C)/ln(a)

Total delay along the chain D = Total inverters along the chain * Delay of each inverter.

Earlier we learned that for a back to back inverters where driver inverter input gate capacitance is ‘C’ and the fanout ration of ‘a’, the delay through driver inverter is 3aRC

Total delay along the chain D = ln(CL/C)/ln(a) * 3aRC

If we want to find the minimum value of total delay function for a specific value of fanout ‘a’, we need to take the derivative of ‘total delay’ with respect to ‘a’ and make it zero. That gives us the minima of the ‘total delay’ with respect to ‘a’.

D = 3*RC*ln(CL/C)*a/ln(a)

dD/da = 3*RC* ln(CL/C) [ (ln(a) -1)/ln2(a)] = 0

For this to be true

(ln(a) -1) = 0

Which means : ln(a) = 1, the root of which is a = e.

This is how we derive the fanout of ‘e’ to be an optimal fanout for a chain of inverters.
If one were to plot the value of total delay ‘D’ against ‘a’ for such an inverter chain it looks like following.

Figure 5. Total delay v/s Fanout graph

As you can see in the graph, you get lowest delay through a chain of inverters around ratio of ‘e’. Of course we made simplifying assumptions including the zero diffusion capacitance. In reality graph still follows similar contour even when you improve inverter delay model to be very accurate. What actually happens is that from fanout of 2 to fanout of 6 the delay is within less than 5% range. That is the reason, in practice a fanout of 2 to 6 is used with ideal being close to ‘e’.

One more thing to remember here is that, we assumed a chain of inverter. In practice many times you would find a gate driving a long wire. The theory still applies, one just have to find out the effective wire capacitance that the driving gate sees and use that to come up with the fanout ratio.

-SS.

Last stage to consider in this series of posts is when inverter input is high. Following figure shows this condition.

Figure 1. Inverter with input at VDD.

You can easily tell that pmos gate to source voltage difference is zero. Both are at VDD, hence pmos can not be active, it can only be in saturation or cut-off depending upon the node ‘out’ voltage.

Nmos gate is at VDD and gate to source is forward biased and channel is formed. If node ‘out’ was at VDD to begin with, nmos would start out in saturation as gate to drain would have been cut-off and as node ‘out’ continues to discharge, the nmos would enter linear region and would remain there for rest of discharge. On the other hand pmos would start out in cut-off region with both junction cut-off and would remain so for rest of the time.

Will discuss few popular questions with answer in next series of posts.

-SS

Previously we looked at the transistor modes during inverter operation, when input is at VSS. Now lets look at the transistor modes when input is rising and is in the range Vth to VDD – Vth.

Figure 1. Transistor modes in inverters.

We can see that for nmos gate voltage is higher than Vth and source being at VSS, the Vgs for nmos is greater than Vth and inversion channel is formed at gate to source junction. How about gate to drain junction. Again it will depend on what the initial voltage is at node ‘out’. If node ‘out’ voltage is such that Vgd is higher than Vth, the inversion channel extends to gate to drain junction for nmos and nmos is in linear region. But if node at ‘out’ is equal or greater than input/gate voltage for nmos the Vgd is going to be less than Vth or in other words Vds is going to be greater than Vgs – Vth and the gate to drain junction is going to be in cut-off, with pinched off channel and hence nmos in saturation.

When input is rising for an inverter, most likely the node ‘out’ is going to close to VDD to begin with and node ‘out’ will be discharged through nmos, hence to begin with the nmos is going to be in saturation and then it’ll flip to linear region as discharge of ‘out’ continues.

Lets look at the pmos now. Given that Vin is less than VDD – Vth, pmos gate to source junction has inversion channel formed. Again gate to drain for pmos will depend and if node ‘out’ is close to VDD, the gate to drain junction will also have inversion channel formed, which means pmos is going to start out in active region (assuming ‘out’ to be at VDD to begin with) and very soon ‘out’ will match with Vin and fall below Vin, which means gate to drain junction will be cut-off and pmos will flip to saturation.

Keep in mind well that nmos being in active or saturation all along is the reason, current will continue to fall through the nmos and node ‘out’ will discharge. But we also noticed that pmos is also conducting all along, which mean there could be current contention at node ‘out’ and depending upon which one is the stronger source and sink of current, will decide how fast node ‘out’ discharges.

Another thing to notice is that for this range of input voltage Vin, both transistors are on. When pmos or nmos is on, it provides very low resistive path. We have a very low resistive path from VDD to VSS !! What does it mean ? It means a large current would from from VDD to VSS, which is also called crowbar current or rush-through current. Such current could be very damaging to circuit and causes excessive power dissipation.

This is the reason, we want inverter to be in this range for least amount of time possible.  Given the finite rise time of input signals it is inevitable to avoid this region, but one should take care to minimize this region. What can you do to minimize the time inverter stays in the region where input voltage of inverter is within the range Vth to VDD – Vth ??

-SR

In previous post I posed a question as what modes pmos and nmos transistors are during normal inverter operation. Lets answer this question.

For the inverter input we can consider three different possibilities. Lets call input Vin.

case 1) VSS <= Vin < Vth

case 2) Vth < Vin < (VDD – Vth)

case 3) (VDD – Vth) < Vin <= VDD

Figure 1. Inverter charging output node high

It will become apparent later on as to why we choose these ranges. Lets think of first case where input is between the range VSS and Vth. For nmos device, source is tied to ground and if gate voltage is less than Vth we know gate to source junction is cut-off. What about gate to drain junction of nmos ? We don’t know initial voltage at node ‘out’. It could be anywhere between VSS and VDD, but it doesn’t matter, no matter what voltage node ‘out’ is, nmos gate to drain junction is also cut-off as gate voltage is less than Vth. In other words, no matter what voltage node ‘out’ (drain of nmos) is, Vds will always be greater than or equal to (Vgs – Vth) [ Because in this case Vgs is at most Vth, hence (Vgs – Vth) can at most be zero and Vds can not be less than zero ].

Given that both nmos junction are cut-off, there is no channel formed in nmos and nmos is in cut-off for sure.

What about pmos ? Pmos source is tied to VDD and pmos gate is at VSS, hence pmos Vgs is < (VDD – Vth) and channel is formed at pmos gate to source junction. At least one end channel formed, so pmos is definitely not in cut-off. As mentioned earlier node ‘out’ could be at any unknown voltage at initial stage between VSS and VDD. Essentially pmos could be either in active region or saturation and it will start conducting current and start charging the load capacitance it sees at node ‘out’.

If node ‘out’ initial voltage is VSS, the gate to drain voltage difference is zero for pmos and no channel is formed at gate to drain junction for pmos and hence pmos will be in saturation. Remember key to a transistor being in saturation is having a pinched off channel, the channel that is formed only at one of the junctions.

As soon as node ‘out’ reaches Vth or above, or to be more precise the voltage difference the gate to drain voltage difference will reach Vth, the channel will extend at this junction as well. In other words as soon as (Vgs + Vth) < Vds, the pmos will have inversion channels at both junctions and pmos will be in active or ohmic region now. Now onwards drain voltage( node ‘out’ voltage) is only increasing as pmos continues to charge the output load, hence pmos will remain in active region for rest of the time. It will only go back to saturation only if Vgd for pmos increases to more than -Vth.

We conclude that for the case where input voltage of inverter Vin is between VSS and Vth, the nmos is in cutoff and pmos could be either in saturation or active region, but in normal scenario it will be transitioning from saturation to active region.

We’ll consider case 2 & 3 in next post. Please watch for the next post. Your feedback and comments are always appreciated and are most welcome.

-SR

When you think of operation of an inverter, we usually think of input and output binary states. Meaning, we know that if input is low, output is going to be high and vice versa. It might be worthwhile to think, what modes transistors are in during the steady state of inverter and during transition from low to high and vice versa. Transistor modes being, cutoff, linear and saturation. This is a different perspective of looking at the MOS transistor operations in logic gates, which is helpful in getting better overall understanding of MOS circuits.

Lets start with a case where input is low for an inverter as shown in figure below. If input is low (VSS) we know that NMOS Vgs is zero. Because both gate and source are at VSS, which means Vgs < Vth and NMOS is in cutoff. What about PMOS ?

Figure 1. Inverter with input at VSS

We shall discuss the answer in next post. Feel free to comment about your ideas.

-SR.

One of the most important property of a MOS transistors to get a very good handle is its current response. The dependence of the current passing through MOS transistor on the Gate to Source voltage (Vgs) and Drain to Source voltage (Vds).

Following is a fairly popular graph of I v/s V curves of a MOS transistor. Along with the image is shown the setup to achieve the measurements for this I v/s V graph.

Figure 1. NMOS Drain current v/s Drain to Source Voltage at various Gate to Source Voltages.

Figure 2. Spice setup to achieve NMOS I v/s V curves.

Figure 1 depicts two distinct regions of the curve. Linear region and saturation region. In reality there are three regions in this curve: cutoff region, linear region or often referred to as triode region and saturation region. For simplicity most of the curve only shows linear region and saturation region.

These three regions on the curves correspond to the three modes of operation of a MOS transistor. We all know that MOS transistor has three modes cutoff, linear and saturation. Cutoff region on the curve lies very near the origin of the graph.

The curves in figure 1, are achieved through setup in figure 2. You control both Vgs and Vds through variable voltage sources and although it is not shown explicitly in figure 2, you measure Ids passing through transistor.

When gate to source voltage Vgs is less than Vth, the inversion channel has not been formed. Lets recap a bit here for proper reference. In an NMOS transistor, when gate voltage is increase to more than zero, the positive holes in the p substrate are pushed away from the gate by electric field of the same charge(same charge repels eachother).

Figure 3. NMOS transistor modes.

The field at gate not only pushes away the same charge, but also attracts opposite charge electrons near the gate. In p-substrate there are always minority carrier electrons are present. As they are minority they’re not many of them available and the gate field needs to be strong enough to accumulate enough of minority carriers near the gate such that this accumulated set of electrons can effective flow as material current. This happens when gate to source voltage reaches Vth. Until then transistor just doesn’t conduct irrespective of drain to source voltage and it is in cutoff mode

Once gate to source voltage reaches Vth, the inversion channel forms. Now the inversion channel is a lateral channel which could extend from the gate to source and how much it extends towards the drain, really depends on drain voltage. If drain to source voltage Vds is less than (Vgs-Vth), which really means if gate to drain voltage is higher than Vth[ Vds < Vgs – Vth => Vth < Vgs – Vds => Vth < Vgd], the channel extends all the way from source to drain and is called fully formed.

When channel is fully formed, MOS transistor acts like a resistor with linear characteristics. Meaning the current flowing through transistor Ids, linearly varies with Vds, which can be seen in the linear region portion of the curves. This part is often called ohmic region because transistor acts as a ohmic resistor. The reason why transistor behaves linearly in this region, is that the mechanism by which the current travels through transistor in this region is same as in any other resistor.

You can see in the graph that in linear region, Ids increases almost linearly with Vds. Also notice that Ids also depends on the Vgs and increasing Vgs also increases Ids, while maintaining the Ids to Vds relationship.

As you keep increasing Vds, Vds becomes equal to Vgs – Vth, and eventually when Vds becomes more than Vgs – Vth, the channel pinches off at gate to drain junction. This happens because Vgd becomes less than Vth now[ Vds > Vgs – Vth => Vth > Vgs – Vds => Vth > Vgd => Vgd < Vth]. At this stage current flowing mechanism changes inside transistor. There is no more fully formed channel now. This means it doesn’t behave like a resistor anymore and Ids doesn’t change linearly with Vds now.

What happens in this region is that electrons now travel through inversion channel, until the channel ends, and then it travels through depletion region to cross the gate to drain junction. You imagine as if electron dispersion happens and the crossing of electrons through gate to drain junction happens with influence of a different kind of field compared to fully formed channel(attempt at explaining this phenomenon in simple terms). Because of this change in mechanism, current no longer depends on Vds. It still is modulated by Vgs as Vgs dictates how much charge is concentrated in inversion channel at gate to source junction. Please provide your feedback through comments.

-SR.

Following is the case with gate tied to VSS for the nmos. Let’s look at the first transistor on the left side.

For this transistor top end is at VDD and gate is at VSS, which means top end junction is cut-off, remember for nmos junction to be not cut-off the gate to terminal voltage difference has to be > vth. In our case voltage difference between gate to the top end terminal is negative. As usual for bottom end terminal we can assume it to be either VSS or VDD. In either case gate to bottom end voltage difference is going to be less than Vth. Hence both top end and bottom end junctions are going to be cut off and transistor is going to be turned off. One can argue what if node ‘d’ initial value is intermediate between VSS and VDD, even in that case the gate to bottom end voltage difference is going to be less than Vth and still transistor is going to be off.

Let’s consider transistor on the right side. You can see that top end is going to be cut-off as gate to top end voltage difference is zero which is less than Vth. Bottom end situation is going to be same as first transistor. This transistor is going to be off, no current will flow through either of transistors and node ‘d’ will maintain it’s initial state.

Any comments ? Questions ?

-SR