Lets start with the equation of a 2:1 MUX, with input pins A and B, select pin S and output pin Out.

Out = S * A + (S)bar * B

We need to come up with a NAND gate and equation of a NAND gate is of the form :

Out = (A * B)bar or Our = (A)bar + (B)bar [ using De Morgan’s rule]

Given the form of equations that we have to begin with it looks like we might have a better shot of converting. This is purely a guess.

Out = S * A + (S)bar * B to the latter form of NAND equation [ Out = (A)bar + (B)bar]

If we actually tie (A)bar instead of A pin to the MUX and if we tie 1 to the B input

Out = S * (A)bar + (S)bar * 1

Out = S * (A)bar + (S)bar

Now lets prove that this is same as Out = (A)bar + (S)bar

Out = S * (A)bar + (S)bar

(Out)bar = (S * (A)bar + (S)bar) bar

(Out)bar = (S * (A)bar)bar * ((S)bar)bar

(Out)bar = (S * (A)bar)bar * S

(Out)bar = ((S)bar + ((A)bar)bar) * S

(Out)bar = ((S)bar + A) * S

(Out)bar = (S)bar * S + A * S

(Out)bar = 0 + A * S

(Out)bar = A * S

Out = (A * S)bar

Our guess worked and we have a NAND gate by tying (A)bar instead of A and tying B to 1.

Figure NAND using 2:1 MUX

We will look at NOR gate in next post.

-SS