Last stage to consider in this series of posts is when inverter input is high. Following figure shows this condition.
Figure 1. Inverter with input at VDD.
You can easily tell that pmos gate to source voltage difference is zero. Both are at VDD, hence pmos can not be active, it can only be in saturation or cut-off depending upon the node ‘out’ voltage.
Nmos gate is at VDD and gate to source is forward biased and channel is formed. If node ‘out’ was at VDD to begin with, nmos would start out in saturation as gate to drain would have been cut-off and as node ‘out’ continues to discharge, the nmos would enter linear region and would remain there for rest of discharge. On the other hand pmos would start out in cut-off region with both junction cut-off and would remain so for rest of the time.
Will discuss few popular questions with answer in next series of posts.