Transistor modes during inverter operation. Rising input.

Previously we looked at the transistor modes during inverter operation, when input is at VSS. Now lets look at the transistor modes when input is rising and is in the range Vth to VDD – Vth.

Figure 1. Transistor modes in inverters.

We can see that for nmos gate voltage is higher than Vth and source being at VSS, the Vgs for nmos is greater than Vth and inversion channel is formed at gate to source junction. How about gate to drain junction. Again it will depend on what the initial voltage is at node ‘out’. If node ‘out’ voltage is such that Vgd is higher than Vth, the inversion channel extends to gate to drain junction for nmos and nmos is in linear region. But if node at ‘out’ is equal or greater than input/gate voltage for nmos the Vgd is going to be less than Vth or in other words Vds is going to be greater than Vgs – Vth and the gate to drain junction is going to be in cut-off, with pinched off channel and hence nmos in saturation.

When input is rising for an inverter, most likely the node ‘out’ is going to close to VDD to begin with and node ‘out’ will be discharged through nmos, hence to begin with the nmos is going to be in saturation and then it’ll flip to linear region as discharge of ‘out’ continues.

Lets look at the pmos now. Given that Vin is less than VDD – Vth, pmos gate to source junction has inversion channel formed. Again gate to drain for pmos will depend and if node ‘out’ is close to VDD, the gate to drain junction will also have inversion channel formed, which means pmos is going to start out in active region (assuming ‘out’ to be at VDD to begin with) and very soon ‘out’ will match with Vin and fall below Vin, which means gate to drain junction will be cut-off and pmos will flip to saturation.

Keep in mind well that nmos being in active or saturation all along is the reason, current will continue to fall through the nmos and node ‘out’ will discharge. But we also noticed that pmos is also conducting all along, which mean there could be current contention at node ‘out’ and depending upon which one is the stronger source and sink of current, will decide how fast node ‘out’ discharges.

Another thing to notice is that for this range of input voltage Vin, both transistors are on. When pmos or nmos is on, it provides very low resistive path. We have a very low resistive path from VDD to VSS !! What does it mean ? It means a large current would from from VDD to VSS, which is also called crowbar current or rush-through current. Such current could be very damaging to circuit and causes excessive power dissipation.

This is the reason, we want inverter to be in this range for least amount of time possible.  Given the finite rise time of input signals it is inevitable to avoid this region, but one should take care to minimize this region. What can you do to minimize the time inverter stays in the region where input voltage of inverter is within the range Vth to VDD РVth ??


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