Strong ‘0’s and Weak ‘1’s

In the previous post I posed the question as to what the voltage level would be at ‘d’ node in both of the following cases.

Let’s look at the nmos transistor on the left side. Top end(source or drain ?) is at VDD and gate of this device is at VDD. It is obvious that gate to top-end voltage difference for the nmos transistor on the left end side is zero, which is less than the Vth as Vth is typically few hundreds of mili-volts. Based on our understanding of CMOS theory, top-end junction is in cut-off region with no inversion channel formed.

What about the other junction? That is the gate to lower-end junction. We don’t know initial voltage at ‘d’ node, it is unknown to us and it could be anything. Because of that the gate to low-end junction could have fully formed channel if the gate to low-end difference is more than Vth or it could be cut-off if difference is less than Vth.

Now lets take the case where initial voltage at node ‘d’ is VDD, in which case, gate to this bottom-end voltage difference is zero and this junction is cut-off as well. With both junctions at cut-off, transistor is off and no current flows through transistor. Which means top-end voltage remains at VDD and bottom end voltage remains at it’s initial voltage which is VDD as well.

Now what if node ‘d’ is initially at (VDD-Vth) or lower voltage ? In that case gate to bottom-end junction voltage difference is more than Vth and this junction has inversion channel fully developed. Now we know that when at least one junction is on, the current flows through the transistor. In this case gate to top-end junction is off and gate to bottom-end junction is on, which means transistor is in saturation region and current flows from top-end to bottom-end. What would happen is that, if initial voltage at ‘d’ was less than (VDD-Vth), because of the on transistor, the node ‘d’ will keep charging until it reaches at (VDD-Vth), but right when node ‘d’ reaches (VDD-Vth) the bottom junction will be cut-off as at that point the gate to bottom-end voltage difference will become less than Vth

So you can see that for nmos, when one of the end is at VDD, voltage we can never pass more than (VDD-Vth) voltage to the other end. Which we refer to as weak ‘1’ as it doesn’t fully reach VDD. On the other end of one end of nmos is at VSS, we can fully pass this VSS to the other end as we saw in the case of the nmos on the left side.

I’ll ask you same question which asked for pmos example. What would change if nmos input was VSS.


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  1. Pingback: can someone please explain the concept of weak 0 and weak 1?

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