In last post the question was posed, what would happen if pmos input were to be VDD. Let’s examine that.
For the pmos on left, the gate and top-end potentials(voltages) are same, both VDD, which means that junction is definitely cut-off. Now what about initial potential for node ‘d’ ? If we were to assume that our initial voltage could only be within the range of VSS to VDD.
Given this assumption, highest voltage bottom-end node ‘d’ could be at is VDD and even then the bottom-end junction will be cutoff as gate and the node ‘d’ would both be at same voltage VDD. If node ‘d’ is at lower voltage than VDD, the junction is still going to be cutoff as in either case gate voltage is going to be higher than the bottom-end voltage and for pmos inversion channel to be formed, the gate voltage has to be lower than the junction voltage by Vth.
So pmos on the left side will always be off, there will be no current passing through this pmos and it will not contribute to any change in initial voltage at node ‘d’.
Reader should be able to extrapolate what would happen to the pmos on the right. Is it going to be same as pmos on left or any different ?
As always, your questions and comments are welcome.