In the previous post I posed the question as to what the voltage level would be at ‘d’ node in both of the following cases.
Let’s look at the pmos transistor on the left side. Top end(source or drain ?) is at VDD and gate of this device is at VSS. It is obvious that gate to top-end voltage difference for the pmos transistor on the left end side is(VSS) less than the (VDD-Vth) as Vth is typically few hundreds of mili-volts at the most. Based on our understanding of CMOS theory, inversion channel has fully formed at the gate to top-end junction. Now pay attention closely, you will not get this information at anywhere else if you’re just beginning to learn CMOS transistors.
At this stage you might wonder, what about the other junction. That is the gate to lower-end junction. We don’t know initial voltage at ‘d’ node, it is unknown to us and it could be anything. Because of that the gate to low-end junction could have fully formed channel if the gate to low-end difference is less than (VDD-Vth) or it could be cut-off if difference is more than (VDD-Vth).
In either case there is a low-resistance conduction path formed from top-end of this transistor to bottom-end. Why ? Because if both junctions have fully formed channel, it’s obvious there is a path, but even when bottom-end channel is cut-off( also called pinched-off) the carriers still drift through this pinched-off junction under the effect of the electrical field and node ‘d’ keeps getting charged and it’ll get fully charged upto VDD without any problems. It can not go above VDD as that’s when it reaches same potential as the top-end node.
So eventually node ‘d’ for the pmos transistor on left will settle at VDD.
I intentionally refereed to nodes as ‘top-end’ and ‘bottom-end’ as in reality source and drain are reversible for a transistor, but by convention the source is the source of the current carries(electrons) and drain is the node that receives electron. In our case the current follows from top to bottom, which means electrons travel from bottom to top and hence bottom-end is source and top-end is drain.
Now what about pmos transistor on the right side. As you can imagine, the gate to top-end voltage difference is zero ( both at VSS), which means this junction is cut-off. Gate of the pmos transistor needs to be less than one of the ends by Vth amount in order for the channel to form at that junction.
How about initial voltage at node ‘d’. Again, we don’t know what it could be. But what we know is that as long as it’s more than Vth, the gate to bottom-end junction channel will form and as long as one junction channel forms, the current will flow. The key is node ‘d’ can never fall below Vth, because right when it reaches a fraction below Vth, that junction channel will be cut-off and we know that gate to top-end junction channel is already cut-off, and with both junctions cut-off, transistor turns off and no more current can flow through it and no more voltage difference takes place.
So bottom-end in right side transistor can never fall below Vth.
We learn two important lessons about pmos characteristics. If one of the end of pmos is at VDD, we can fully pass VDD level to other end of pmos by biasing gate voltage to be VSS. But if one of the end of pmos transistor is at VSS, no matter what you do you can not bias other end to VSS, other end can not fall below Vth.
We say that pmos passes strong ‘1’ (VDD) but it can only pass weak ‘0’ (VSS).
What would happen if the gate is at VDD in both cases ?
Excellent explanation, thnks for you valuable share.