Wire Delay Modeling for Static Timing Analysis.

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In previous post we saw how we use a look-up table based simple modelling of devices for getting timing-arcs or delay-arcs through the devices. These arcs are nothing but input-output pin pair delay values. Now we can look at how wire delays are modeled in STA.

In spice modelling, again wires are represented through a complex mathematical function based models are used ( Think matrices, nodal analysis ), which accurately models wires behavior and you can see waveform propagation happening through wires based on the characteristics of the wires and one can measure delays through probing the waveforms in question during the dynamic timing analysis.

Similar to devices, idea is to come up with a simplistic modelling of wires which can give us reasonably accurate delay values through the wires, for static timing analysis. There are several models available for wires, but one such model ‘Elmore delay’ has been widely used in industry because of its simplicity and relative accuracy. We’ll talk more about this Elmore delay model here.

If you want to find out wire delay from point ‘a’ to point ‘c’, we can get it using following formula.
RC(ac)= R1C1 + (R1+R2)C2.
If there are N stages, general formula is like following.
RC(an)= R1C1 + (R1+R2)C2 + (R1+R2+R3)C3 + … + (R1+R2+R3+….+RN)CN.

Hope you get the idea.

In practice any segment of wire is broken into small pieces, like the R1, R2.. RN in the picture and Elmore delay formula is used to come up with the real wire delay numbers. Here I’ve explained very simplified concept of the wiredelay. Later on we’ll discuss more about various complexities that we’ve to deal with when we want to accurately come up with wire delays.


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