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In timing analysis we are interested in mainly delay through standard gates and slopes or transition values of signals at various nodes in circuit. These delays and slopes dictate what speed your circuit will run without any functional issues.STA stands for Static Timing Analysis. Static as opposed to dynamic timing analysis. One can choose to do either static or dynamic timing analysis. So what is the difference ?

Main difference between two methods lies in the way circuit components are modeled. Dynamic timing analysis is done through dynamic simulation of the circuits. Spice simulation that you might be familiar with. While static timing analysis is done through a look-up table method, no dynamic simulation is performed.

For standard cells(logic gates), delay through the cell primarily depends on three factors: Strength of the cell, input signal slope and output pin load.

For dynamic analysis spice simulation of the whole circuit in question is carried out. In spice simulation circuit devices are modeled through mathematical functions. Think of matrices and nodal analysis. To state in simple terms, spice model has mathematical functions of various parameters of the device.

A standard cell is modeled through math functions where by delay through the cell is represented as a function of the input signal slope, output pin load and the strength of the cell in question.

If you look at the following simple figure of a buffer, it’ll be provided input wave from with certain slope and on output a waveform with certain slope will be observed. The delay of the cells is measured through these wave forms at 50% rise/fall time as shown in the picture.

While in static timing analysis, we don’t simulate, but the device behavior is represented as a table and based on the actual input parameter values we just look up the table to find delay through the cell.
Lets say the size of buffer in above figure is B and for this B size we’ve following extensively simplified version of the table.

Input Slope	Output Load	Delay
0.05ns	0.2pf	0.05ns
0.1ns	0.2pf	0.075ns

As it was mentioned previously the delay through the cell depends on the input waveform slope and output pin load. When the timing analysis is done, based on the current values of input slope and output load we simply pick the correct entry from the table there we’ve delay number through the cell. That simple !

Of course this is simplistic analysis to give you a very high level idea of the difference between static v/s dynamic timing analysis.

So what about wires in the circuit ? That we’ll cover in next post.

Looking for interview questions? Preparing for interview in VLSI field ? Get most frequently asked Static Timing Analysis Interview quetsions