In last post we looked at general signal propagation from one flop to another and we talked at higher level of max delay or setup constraint. Let’s look at max delay constraint in more depth so it is very clear before we move onto min delay or hold constraint.
Following figure describes visually a setup failure. As you can see that first flop releases the data at the active edge of clock, which happens to be the rising edge of the clock. FF1_out falls sometime after the clk1 rises.
The delay from the clock rising to the data changing at output pin is commonly referred to as clock to out delay. There is finite delay from FF1_out to FF2_in through some combinational logic for the signal to travel. After this delay signal arrives at second flop and FF2_in falls. Because of large delay from FF1_out to FF2_in, FF2_in falls after the setup requirement of second flop, indicated by the orange/red vertical dotted line.
This means input signal to second flop FF2_in, is not held stable for setup time requirement of the flop and hence this flop goes meta-stable and takes a long time before settling to the correct value. In theory it could take upto one clock cycle or even more than a clock cycle to resolve the meta-stability, which means flop output could be in the unknown state for one full clock cycle or even more. This means down stream logic( down stream flop or latches) capture wrong data and your state machine is corrupted.
As you can see one would’ve expected ‘Out’ node to go low but it doesn’t because of setup time or max delay failure at the input of the second flop. Setup time requirement dictates that input signal be steady during the setup window ( which is a certain time before the clock capture edge ).
Another possibility is that if input FF2_in, doesn’t fall(change) near the closing edge of the flop, but because of very large delays from FF1_out, it just falls much later than the second rising edge of the clock, in which case, the second flop wouldn’t go meta-stable, but it will just capture ‘1’ to the input, which would be a wrong value to be captured and could cause downstream functional failure.
As mentioned earlier if we reduce frequency, our cycle time increases and eventually FF2_in will be able to make it in time and there will not be a setup failure. Also notice that a clock skew is observed at the second flop.
The clock to second flop clk2 is not aligned with clk1 anymore and it arrives earlier, which exacerbates the setup failure. This is a real world situation where clock to all receivers will not arrival at same time and designer will have to account for the clock skew. We’ll talk separately about clock skew in details in later posts.